1. Field of the Invention
The invention relates to a MASH modulator and, in particular, to a MASH modulator with fewer logic circuits to improve fractional spur thereof.
2. Description of the Related Art
To satisfy the demands of multi-mode frequency planning, fractional synthesizers have been widely used for local oscillator (LO) frequency generation in wireless applications. However, such fractional synthesizers suffer serious fractional spur problems in output spectrum thereof. For example, in a case of small fractional number, the fractional spur cannot be filtered out by a loop filter in a phase locked loop (PLL) of the fractional synthesizer, and will remain in-band. For multi-mode frequency planning, the small fractional number is not avoidable and the non-filtered spur impacts system performance significantly. To solve this problem, conventionally, sigma delta modulators (SDMs) are adopted in frequency synthesizers. The fractional spur will be suppressed as the order of the SDM increases. Generally, SDMs of an order higher than 2 are widely used.
Another cause of the fractional spur is nonlinearity in the PLL. The nonlinearity could result from timing mismatch in a phase frequency detector (PFD) or current mismatch in a charge pump. When the frequency synthesizer uses a high order SDM, the mismatch between UP/DN currents of the charge pump becomes a major cause of fractional spur. To keep the fractional spur low, demands on current matching are stringent. With 5% current mismatch, the in-band fractional spur might be greater than −40 dB below a carrier.
FIG. 1 is a block diagram of a conventional MASH modulator. The conventional MASH modulator comprises three cascaded first order sigma delta modulators (SDMs). The input of the next stage SDM is the quantization noise of the previous stage SDM. The quantization noises of the intermediate stage SDM are then all digitally cancelled. Thus, only the quantization noise from the last stage SDM is left and MASH becomes stable. However, there are still some defects in MASH architecture. For example, the quantization noise cancellation is sensitive to the gain matching accuracy between each stage of MASH. In addition, more operational amplifiers and more capacitors are required in MASH than in classical architecture such that the chip size of MASH increases. The MASH modulator is often used in a PLL due to inherent stability thereof. In such a MASH modulator, a fractional number is typically synthesized by two integers, 0 or 1. When the fractional number is close to 0 or 1, the MASH SDM outputs almost 0 or 1, respectively. Thus, the in-band fractional spur will remain inband due to nonlinearities of the PLL and cannot be attenuated by a filter thereof.